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6.2 Deﬁning a Clock Period

In the above example, no constraints were given and the SYNOPSYS DESIGN COMPILER synthesized the design with the

minimum possible effort. The synthesis tool is able to extend its efforts to meet the speciﬁed timing constraints. Let us

have a look at what happens if we constrain the clock period of the circuit

Remove the last design and start from scratch.

dcs > remove_design -all

dcs > analyze -format vhdl ../sourcecode/datapath.vhd

dcs > elaborate datapath

The following command sets the clock period to 1 ns.

dcs > create_clock Clk_CI -period 1.0

Now, we compile the circuit.

dcs > compile

This time, the SYNOPSYS DESIGN COMPILER will try to come up with a netlist that meets the constrained clock period of

1 ns.

Student Task 5: Examine the resulting circuit by using the appropriate reporting commands. What is the effective

clock period and the required area now?

A =

As one can see, the area is enlarged while the timing constraint is met. Furthermore, with the use of the command

report_reference, one can observe that the variety and specialization of the components has increased.

If you have investigated the timing reports of both the unconstrained and the constrained design in detail, you may have

recognized that the reported paths are different. Therefore, let us have a closer look at the different timings within a

sequential circuit.

6.3 Diﬀerent Timing Paths

As depicted in Figure 7, the data paths of a sequential circuit can be subdivided into four categories with regard to their

timings:

o(k)

s(k)

i(k)

s(k+1)

combinational

circuitry

state register

CLK

present

input

present

output

present

state

: From state-holding registers to state-holding registers (s → s),

: From input to state-holding registers (i → s),

: From state-holding registers to output (s → o)

: From input to output (i → o).

Figure 7: Signal propagation paths through single-phase edge-triggered synchronous circuits.

Please refer to the VLSI 1 lecture notes for further information on timings.

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